Pnpn impatt diode having unequal electric field maxima

ABSTRACT

This invention relates to a high-frequency semiconductor device wherein the internal built-in electric field distribution in a semiconductor is made to have two peak values under a DC bias condition and an avalanche multiplication effect in the semiconductor is used to obtain a high-efficiency oscillation in a high-frequency region.

United States Patent Mizushima et al.

[451 Jan. 25, 1972 PNPN IMPATT DIODE HAVING UNEQUAL ELECTRIC FIELD MAXIMA Yoshihiko Mizushima; Kawarada, both of Tokyo, Japan Inventors: Kuniyasu Assignee: Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan Sept. 19, 1969 Filed:

Appl. No.:

Foreign Application Priority Data Sept. 21, 1968 Japan ..43/68123 US. Cl ..317/235 R, 317/235 K, 317/235 T,

317/235 AA, 317/235 AB, 317/235 AD lnt.Cl ..H01l9/10,H0119/12,H01111/10 Field of Search ..317/235 K, 235 T, 235 AA, 235 AB References Cited UNITED STATES PATENTS 7/1959 Weinreich ..332/52 3,284,639 1 H1966 Giuliano et al. ..317/235 AD UX 3,356,866 12/1967 Misawa ..317/235 AD UX 3,426,295 2/1969 De Loach et a1. ..331/107 3,566,206 2/1971 Bartelink et a1. ..317/234 Primary Examiner--John W. H uckert Assistant ExaminerWi11iam D. Larkin Attorney-Watson, Cole, Grindle & Watson 5 7] ABSTRACT This invention relates to a high-frequency semiconductor device wherein the internal built-in electric field distribution in a semiconductor is made to have two peak values under a DC bias condition and an avalanche multiplication effect in the semiconductor is used to obtain a high-efficiency oscillation in a high-frequency region.

8 Claims, 6 Drawing Figures PNPN IMPAT'I DIODE HAVING UNEQUAL ELECTRIC FIELD MAXIMA SUMMARY OF THE INVENTION This invention relates to a high-frequency semiconductor device wherein semiconductor elements are used to obtain a high-frequency oscillation output. BACKGROUND OF THE INVENTION There are known high-frequency semiconductor devices wherein semiconductor elements having a PN-junction are utilized to obtain a high-frequency oscillation output. It utilizes an avalanche carrier multiplication phenomenon caused within semiconductor elements by impressing a backward bias on a PN-junction. In case of semiconductor elements having such conventional single PN structure, however, in order that the space charge effect on the internal built-in field of the semiconductor elements may be effective as an important factor in high-efficiency operation, a high current density is required. Therefore, such devices have the disadvantage that their oscillation efficiency is low because of the absence of a high current density.

Therefore, an object of the present invention is to provide an improved high-frequency semiconductor device wherein a high-frequency output is obtained with high efficiency by using a combination of single PN-junctions.

The high-frequency semiconductor device according to the present invention is characterized by a semiconductor device comprising a PNPN-structure extending between first and second electrodes wherein an optimum internal electric field distribution is created at regions in the semiconductor device so that initially one PN-junction has an electricfield which in duces avalanche breakdown and the other PN-junction has an electric field which is just below the avalanche point. Carriers from the first junction migrate to the second junction and cause the electric field distribution across that junction to increase above the threshold of the avalanche breakdown. Carriers from the second junction migrate to the first junction and increase the weakened electric field distribution (caused by the former carrier migration) to reestablish avalanche breakdown at the first junction and initiate the cyclic migration ,of carriers described above. A high-frequency oscillation results from the avalanche carrier multiplication and carrier transit time effects. In the present invention, the above described internal electric field distribution having optimum values at the two regions in the semiconductor device is called a dual-peak field distribution.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an embodiment of the highfrequency semiconductor device according to the present invention.

FIG. 2 is a field distribution diagram for explaining the operation of FIG. 1.

FIGS. 3 to 6 are diagrams showing other embodiments of the high-frequency semiconductor device according to the present invention.

DETAILED DESCRIPTION FIG. I, represents a semiconductor device wherein a P'- layer L,, N-layer L P-layer L and N-layer L, are arranged in the order mentioned to form junctions 1, I and J the first and second electrodes T, and T are attached to the P-layer L, and N-layer L, respectively, and a DC bias source 3 is connected between the electrodes T, and T through a load 2, for example a resistance, with the electrodes T, and T, respectively biased negatively and positively. The load one may be a resistance, transmission line, or a resonant circuit. For microwave use the resonant circuit can comprise coaxial cavity or a waveguide cavity, and in such cases the semiconductor element may be mounted in the cavity.

Thus, the semiconductor device I has a structure which may be represented as two cascade-connected PN structures.

the junctions 1,, and 1,, of the two equivalent elements and, if the distance D in the direction of the layers L,, L L and L, of the semiconductor device 1 is represented as the abscissa and the electric field strength E within the semiconductor device 1 is represented as the ordinate, as shown in FIG. 2, there will be obtained a dual-peak field distribution curve 4 presenting optimum values substantially in the positions of the junctions 1,, and .l;,,. In such case, the positions in which the optimum values of the dual-peak field distribution curve 4 are obtained can be varied by varying the respective thickness of the layers L,, L,, L, and L,. Further, the magnitude of the values of the curve 4 can be varied by varying the voltage value of the bias source 3.

In casethe position and the value of the optimum peaks in the dual-peak field curve are properly selected, for example as in FIG. 2, wherein the initial field at junction 1,, exceeds the junction avalanche breakdown and the initial field at junction J is less than the junction avalanche breakdown, an avalanche multiplication of the carriers will occur at 1,, first, the avalanche carriers will migrate toward junction 1 and, after the carrier transit time, the optimum value of the electric field at 1;, will be pushed up into the avalanche region by the space-charge effect of the carriers avalanche multiplication at J;,, will be induced and carriers of an opposite polarity will migrate toward junction 1, When such carriers come out of the depletion layer, the terminal voltage will rise again, an

avalanche at 1,, will again occur and thereafter the operation will repeated. The amplitude of the conduction current in-- duced in the external circuit will increase due to the carriers produced by the induced avalanche, the amplitude of the terminal voltage will also increase, and a high oscillation output will be obtained at the load 2. Even in a conventional unit PN structure, a dual-peak field distribution is temporarily formed and an induced avalanche can be produced. To realize such a state, however, a sufficiently high carrier density is required. Taking the influence of heat generation into consideration, it has been difficult to realize continuous operation. On the other hand, in the structure of the present invention, by forming a dual-peak field distribution with a DC bias condition, it is possible to cause an effective modification of the field distribution and an induced avalanche at a relatively low current density.

In fact, with the above-described semiconductor device 1, where the P-layer L was formed by dilTusion on semiconductor N-layer L, having a specific resistance of l Q-cm; to be the N-layer L,, the N-layer L, was diffused on P-layer L,,; P- layer L, was diffused on N-layer; the layers L L and L, were respectively made 2 p, 5 p. and 5 pt thick and were then mesaetched; the cross-sectional area of the layer L, was a cross-sectional area corresponding to a diameter of approximately 200 p. (3.14Xl0t:m. an area corresponding to the junction 1, the layers L, and I, to which the electrodes T, and T were respectively attached were applied and the resulting semicon- 1 ductor device 1 was connected to the load 2 and DC bias source 3 as described above and was mounted in a waveguide; a continuous oscillation output having an oscillation efi'rciency of 26 percent and a frequency of 9 gI-lz at an average current density of 3X10 a./cm. was obtained. What is to be noted here is that the semiconductor device in this example has a PNPN-structure and therefore although the structure is apparently the same as a known conventional semiconductor-controlled rectifier (thyristor), in the latter, a variable bias with alternating polarity is provided to its PN- junction. In contradistinction thereto the semiconductor device 1 according to the present invention has a bias voltage of a fixed polarity so that a dual-peak field distribution is formed within the semiconductor device and oscillation effected by avalanche multiplication and the carrier transit time. If the semiconductor device according to the present invention is combined with microwave circuit elements to operate in a region of such high frequency at which the transit time effect cannot be ignored, the optimum value of the effectively Therefore, if a backward bias is provided from bias source 3 to operating cross-sectional area in the junctions 1, J and J in the semiconductor device 1 is made smaller than an area corresponding to a diameter of 3. l4 l0-cm. and the total length of the active zone is madeless than 40 11.. Such limitations of the cross-sectional area and total length are based on the fact that, in the case of the former, due to the increase of the capacitance between the electrodes T, and T,, the abovedescribed oscillation output will otherwise be no longer obtained and that in the case of the latter, the oscillation frequency will otherwise be reduced to a practically insignificant frequency region. Therefore, the semiconductor device such as the known conventional thyristor and the present invention are also distinguished from each other in the device dimensions such as the cross-sectional area and total length. Therefore, the semiconductor device in this embodiment is characterized in that it has a dual-peak field distribution and also a high-frequency casing to be mounted in a waveguide or strip line; and the maximum cross-sectional area of the junctions J J and 1,, within the semiconductor device is smaller than an area approximately 3.l4Xl0 cm. and their total length is selected to be less than 40 t.

Now, the embodiment in FIG. 3 shall be described. In this embodiment, the semiconductor device 1 is the same as is described above with reference to FIG. 1 except that an I- layer L is inserted between the N-layer L and P-layer L, in the embodiment in FIG. 1 and therefore a junction 1,, between the N-layer L, and I-layer L and a junction J between the I-layer L and P-layer L;, are formed instead of the junction J in FIG. 1. The same corresponding signs are attached to the respective parts corresponding to those in FIG. 1 and detailed explanations of such parts are omitted. This embodiment, too, has aPN structure composed of the P-layer L, and N-layer L, and a PN structure composed of the P-layer L, and N-layer L are cascade connected through the I-layer L Therefore, by properly selecting the thickness of the layers L, to L, including the I-layer L the same operation and efi'ect as described above with reference to FIG. 1 are obtained. In fact, the semiconductor device in this embodiment, where the layers L,, L,, L,,, L, and L, were formed by diffusion in the same manner as in the case of FIG. 1, were the mesa etched and were then made respectively 5 u, 5 p., 20 u, 3 p. and 2 u thick, the cross-sectional area of the layer L, corresponded to an area of approximately 1.75X *cm. or a diameter of 150 p. and then the device was mounted in a waveguide, an oscillation output of about 2.5 gHz was obtained. Now the embodiment in FIG. 4 shall be described. In the embodiment the semiconductor device 1 is the same as is described above with reference to FIG. 1 except that an N- layer L, is arranged on a part of the P-layer L,, a junction J, is formed between the N-layer L, and P-layer L,, a third electrode T; is attached to the N-layer L and a DC or AC control bias source 5 is connected to the electrode T The same corresponding signs are attached to the respective parts corresponding to those in FIG. 1 and detailed explanations of such parts are omitted. However, in this embodiment, the same oscillation output as is described above with reference to FIG. I is minority carriers are injected into the layer L, across the junction 1,, from the bias source 5 to control the oscillating output. For example, if a DC bias is applied by the bias source S and if a pulse signal is applied, an oscillation output synchronized with the pulse signal is obtained. If a gate signal is applied the oscillation is started or stopped by the gate signal. v

Further, the embodiment in FIG. 5 shall be described. In this embodiment, the semiconductor device I is the same as is described above with reference to FIG. 1 except that a P-layer L is arranged on the N-layer L,, a junction 1,, is formed between the P-layer L, and N-layer L,, a third electrode T, is attached to the P-layer L and a control bias source 5 is connected to the electrode T, in the same manner as is described above with reference to FIG. 4. Therefore, the same corresponding signs are attached to the respective parts corresponding to those in FIG. 1 and detailed explanations of such parts shall be omitted. However, as minority carriers are injected into the layer L, across the junction 1,, from the bias source 5, the same operation and effect as are described above with reference to FIG. 4 is obtained. I

Still further, the embodiment in FIG. 6 shall be described. In this embodiment, the semiconductor device I is the same as is described above with reference to FIG. 1 except that the P- layer L, is partly removed and replaced by a P-layer L,,, a junction I is formed between the P-layer L, and N-layer L,, a third electrode T, is attached to the P-layer L, and a control bias source 5 is connected to the electrode T, in the same manner as is described above with reference to FIG. 4. Therefore, the same corresponding signs are attached to the respective parts corresponding to those in FIG. 1 and detailed explanations of such parts are omitted. However, as minority carriers are injected into the layer L, across the junction 1,, from the bias source 5, the same operation and effect as are described above with reference to FIG. 4 is obtained.

In the above description, only a few embodiments of the present invention are shown. It will be obvious, for example, the injection of minority carriers as is shown in FIGS. 4 to 6 can be applied also to the semiconductor device described above with reference to FIG. 3.

However, the main point of this invention is that a semiconductor device is so made as to be able to produce a sufficiently high electric field distribution at two regions in the semiconductor device by applying a required DC bias between the first and the second electrodes to cause an alternating avalanche breakdown at said regions and, in such a state, a high-frequency oscillation output may be obtained on the basis of a carrier multiplication phenomenon by an avalanche and a carrier transit-time effect.

In the above-description, an oscillation output is obtained where the DC bias source 3 is connected only between the electrodes T, and T However, it is also possible to adjust the DC bias just below the threshold necessary to produce an oscillation output and to add another control bias voltage superposed on the first bias through the third electrode to obtain an oscillatory output. In such case, the control bias source may be connected in series with the DC bias source 3. Also the control bias source in this case may consist of pulses.

Further, in the above descriptions, the case has mainly been considered that the oscillation output of a continuous periodic wave is controlled. However, for example, if in the above described DC bias state, a resistive load is connected as the external load 2 and a pulse voltage having a pulse width of about one-half of the oscillation period is applied as an input signal voltage, an amplified output pulse, corresponding one to one to the input pulse, can be delivered to the load and so, the device can operate as a high-speed pulse amplifier. In such a case, no particular consideration is required with respect to the transit-time effect.

What is claimed is:

l. A high-frequency semiconductor comprising:

a semiconductor element having at least four layers of alternating conductivity type and at least three rectifying junctions, the two endmost junctions having unequal reverse breakdown voltages, means for providing a DC voltage bias across said semiconductor element, said bias providing a backward bias to both endmost junction and having a magnitude so that a dual-peak electric field distribution is established across said semiconductor element, one

said peak is at one endmost rectifying junction and the" other said peak is at the other endmost rectifying junction, one of said peaks exceeds the avalanche breakdown of the associated junction and the other said peak is lower than the avalanche breakdown of the other associated junction,

load means connected to said semiconductor element for' receiving the oscillatory output signal from said semiconductor element.

2. A high-frequency semiconductor device as in claim I wherein the effective cross-sectional area of said semiconductor element is less than approximately 3.14Xl0cm. and the distance between the endmost junctions is less than 40 microns.

3. A high-frequency semiconductor device as in claim 1, wherein said rectifying junctions are formed in a cascade arrangement to fonn a PNPN-structure and the electric field at the middle junction is substantially less than the electric field at said endmost junctions.

4. A high-frequency semiconductor device as in claim 1 wherein said semiconductor element further includes an 1 layer to form a PNIPN structure, and the effective cross-sectional area of said semiconductor element is substantially equal to l.75 l-cm.'*'.

5. A high-frequency semiconductor device as in claim 3, wherein said semiconductor element further includes an additional N-layer forming a junction with the end P-layer and said semiconductor device further comprises means for providing a control bias to said additional junction for controlling the oscillatory output of said device.

6. A high-frequency semiconductor device as in claim 3 wherein said semiconductor element further includes an additional P-layer fonning a junction with the end N-layer and said device further comprises means for providing a control bias to said additional junction for controlling the oscillatory output of said device.

7. A high-frequency semiconductor device as in claim 3 wherein the end P-layer is partially removed from the adjacent N-layer thereby forming two separate rectifying junctions, one of said separate rectifying junctions is one of said at least three rectifying junctions, and said device further comprises means for providing a control bias to the other of said two separate rectifying junctions for controlling the oscillatory output of said device.

8. A high-frequency semiconductor device as in claim 4 wherein the layers of said semiconductor element have respective widths of 5 u, 5 u, 20 p, 3 [L and 2 p. 

1. A high-frequency semiconductor comprising: a semiconductor element having at least four layers of alternating conductivity type and at least three rectifying junctions, the two endmost junctions having unequal reverse breakdown voltages, means for providing a DC voltage bias across said semiconductor element, said bias providing a backward bias to both endmost junction and having a magnitude so that a dual-peak electric field distribution is established across said semiconductor element, one said peak is at one endmost rectifying junction and the other said peak is at the other endmost rectifying junction, one of said peaks exceeds the avalanche breakdown of the associated junction and the other said peak is lower than the avalanche breakdown of the other associated junction, load means connected to said semiconductor element for receiving the oscillatory output signal from said semiconductor element.
 2. A high-frequency semiconductor device as in claim 1 wherein the effective cross-sectional area of said semiconductor element is less than approximately 3.14 X 10 4cm.2 and the distance between the endmost junctions is less than 40 microns.
 3. A high-frequency semiconductor device as in claim 1, wherein said rectifying junctions are formed in a cascade arrangement to form a PNPN-structure and the electric field at the middle junction is substantially less than the electric field at said endmost junctions.
 4. A high-frequency semiconductor device as in claim 1 wherein said semiconductor element further includes an I-layer to form a PNIPN structure, and the effective cross-sectional area of said semiconductor element is substantially equal to 1.75 X 10 4cm.2.
 5. A high-frequency semiconductor device as in claim 3, wherein said semiconductor element further includes an additional N-layer forming a junction with the end P-layer and sAid semiconductor device further comprises means for providing a control bias to said additional junction for controlling the oscillatory output of said device.
 6. A high-frequency semiconductor device as in claim 3 wherein said semiconductor element further includes an additional P-layer forming a junction with the end N-layer and said device further comprises means for providing a control bias to said additional junction for controlling the oscillatory output of said device.
 7. A high-frequency semiconductor device as in claim 3 wherein the end P-layer is partially removed from the adjacent N-layer thereby forming two separate rectifying junctions, one of said separate rectifying junctions is one of said at least three rectifying junctions, and said device further comprises means for providing a control bias to the other of said two separate rectifying junctions for controlling the oscillatory output of said device.
 8. A high-frequency semiconductor device as in claim 4 wherein the layers of said semiconductor element have respective widths of 5 Mu , 5 Mu , 20 Mu , 3 Mu and 2 Mu . 